Elitegroup BIOS Free Driver Download (Official)
P5TX-B PCB 2.0, Version 1.1
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1. Set the default value of "Fast RAS to CAR Delay" to be 3 CLKs
2. For supporting Cyrix P200+, adjust DRAM timing at 75 MHz bus speed as follows:
(1) DRAM R/W leadoff: 11/7/4
(2) DRAM Read Burst Timing (FP/EDO): x333/x444
(3) DRAM write Burst Timing: X333
(4) Fast RAS to CAS Delay: 3 CLKs
(5) Fast MA to RAS# Delay: 1 CLKs
(6) SDRAM (CAS/RAS Latency): 3/3
3. Fix code bugs for PCI 32Bit protect mode functions for passing PCIDIAG testing
4. Add Write Allocation support for K6 CPU and change the dislpay string for K6 to "AMD-K6/PR2-XXX" where XXX is the core freq
5. Support M2 CPU become standard feature
6. Disable delay for FASTIO and set reserved bit 1 of RCR7 to 0
7. Disable delay for ADS# and enable C
Sheik (DG Staff Member) on 4/26/2004
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