Cypress Semiconductor DDR Controller Driver Download (Official)
The DDR Controller is a device manufactured by Cypress Semiconductor. This driver - "ddr_controller_for_fullflex_dual_ports_12.zip" - has been downloaded 28 times and is rated 5 out of 5 stars based on 11 reviews. The total disk space used for this update is 5.0 MB.
Video Tutorial: How to Download & Install a Driver
Official Source - Manufacturer Website
Supported Models
DDR Controller
Manufacturers
Supported Operating Systems
Not Applicable
File Name
Additional Notes
DDR Controller
Dual-Ports
Driver File
Uploaded By
Purushothaman (DG Staff Member) on 18-Apr-2006
Related Driver Updates
Driver Contents File List
The following files are found inside the driver download file.
| Name | Size | Date |
|---|---|---|
| ddr_controller/altera_mf.v | 1.3 MB | 17 May 2005 |
| ddr_controller/doc/ddr_controller_user_guide.doc | 215.6 KB | 18 Jul 2005 |
| ddr_controller/doc/xilinx_ddr_controller_user_guide.doc | 214.0 KB | 18 Jul 2005 |
| ddr_controller/functional_rtl/DdrCntrlTop.v | 31.2 KB | 17 May 2005 |
| ddr_controller/functional_rtl/IOBUF.v | 2.4 KB | 17 May 2005 |
| ddr_controller/functional_rtl/bidir_test.v | 6.8 KB | 17 May 2005 |
| ddr_controller/functional_rtl/bidircomp.v | 6.1 KB | 17 May 2005 |
| ddr_controller/functional_rtl/bidircomp_add.v | 6.1 KB | 17 May 2005 |
| ddr_controller/functional_rtl/cmp_state.ini | 2 bytes | 17 May 2005 |
| ddr_controller/functional_rtl/config_ddr.v | 5.0 KB | 17 May 2005 |
| ddr_controller/functional_rtl/cycleCntrl.v | 12.9 KB | 17 May 2005 |
| ddr_controller/functional_rtl/fifo.v | 62.0 KB | 17 May 2005 |
| ddr_controller/functional_rtl/fifoCntrl.v | 9.9 KB | 17 May 2005 |
| ddr_controller/functional_rtl/pll.v | 14.8 KB | 17 May 2005 |
| ddr_controller/functional_rtl/pll_read.v | 10.6 KB | 17 May 2005 |
| ddr_controller/functional_rtl/portCntrlRead.v | 6.3 KB | 17 May 2005 |
| ddr_controller/functional_rtl/portCntrlWrite.v | 24.9 KB | 17 May 2005 |
| ddr_controller/memory/flex72s18_addracc.v | 23.1 KB | 17 May 2005 |
| ddr_controller/memory/flex72s18_definations.v | 53.5 KB | 17 May 2005 |
| ddr_controller/memory/flex72s18_ioctl.v | 43.1 KB | 17 May 2005 |
| ddr_controller/memory/flex72s18_mbox.v | 5.8 KB | 17 May 2005 |
| ddr_controller/memory/flex72s18_memory.v | 52.1 KB | 17 May 2005 |
| ddr_controller/memory/flex72s18_rstlogic.v | 9.3 KB | 17 May 2005 |
| ddr_controller/memory/flex72s18_tasks.v | 24.9 KB | 17 May 2005 |
| ddr_controller/memory/flex72s18_timing.v | 36.3 KB | 17 May 2005 |
| ddr_controller/memory/flex72s18_top.v | 34.2 KB | 17 May 2005 |
| ddr_controller/netlist_rtl/DdrCntrlTop.v | 29.6 KB | 17 May 2005 |
| ddr_controller/netlist_rtl/bidircomp.v | 6.1 KB | 17 May 2005 |
| ddr_controller/netlist_rtl/bidircomp_add.v | 6.1 KB | 17 May 2005 |
| ddr_controller/netlist_rtl/cmp_state.ini | 2 bytes | 17 May 2005 |
| ddr_controller/netlist_rtl/config_ddr.v | 5.0 KB | 17 May 2005 |
| ddr_controller/netlist_rtl/cycleCntrl.v | 12.9 KB | 17 May 2005 |
| ddr_controller/netlist_rtl/fifo.v | 62.0 KB | 17 May 2005 |
| ddr_controller/netlist_rtl/fifoCntrl.v | 9.7 KB | 17 May 2005 |
| ddr_controller/netlist_rtl/pll.v | 14.8 KB | 17 May 2005 |
| ddr_controller/netlist_rtl/pll_read.v | 10.6 KB | 17 May 2005 |
| ddr_controller/netlist_rtl/portCntrlRead.v | 6.3 KB | 17 May 2005 |
| ddr_controller/netlist_rtl/portCntrlWrite.v | 24.9 KB | 17 May 2005 |
| ddr_controller/netlist_rtl/rtl_ddr_controller.asm.rpt | 9.2 KB | 17 May 2005 |
| ddr_controller/netlist_rtl/rtl_ddr_controller.done | 26 bytes | 17 May 2005 |
| ddr_controller/netlist_rtl/rtl_ddr_controller.eda.rpt | 5.9 KB | 17 May 2005 |
| ddr_controller/netlist_rtl/rtl_ddr_controller.fit.eqn | 561.2 KB | 17 May 2005 |
| ddr_controller/netlist_rtl/rtl_ddr_controller.fit.rpt | 580.9 KB | 17 May 2005 |
| ddr_controller/netlist_rtl/rtl_ddr_controller.fit.summary | 551 bytes | 17 May 2005 |
| ddr_controller/netlist_rtl/rtl_ddr_controller.flow.rpt | 4.9 KB | 17 May 2005 |
| ddr_controller/netlist_rtl/rtl_ddr_controller.map.eqn | 486.1 KB | 17 May 2005 |
| ddr_controller/netlist_rtl/rtl_ddr_controller.map.rpt | 115.9 KB | 17 May 2005 |
| ddr_controller/netlist_rtl/rtl_ddr_controller.map.summary | 475 bytes | 17 May 2005 |
| ddr_controller/netlist_rtl/rtl_ddr_controller.pin | 117.6 KB | 17 May 2005 |
| ddr_controller/netlist_rtl/rtl_ddr_controller.pof | 2.1 MB | 17 May 2005 |
| ddr_controller/netlist_rtl/rtl_ddr_controller.qpf | 1.6 KB | 17 May 2005 |
| ddr_controller/netlist_rtl/rtl_ddr_controller.qsf | 6.9 KB | 17 May 2005 |
| ddr_controller/netlist_rtl/rtl_ddr_controller.sof | 1.9 MB | 17 May 2005 |
| ddr_controller/netlist_rtl/rtl_ddr_controller.tan.rpt | 852.4 KB | 17 May 2005 |
| ddr_controller/netlist_rtl/rtl_ddr_controller.tan.summary | 4.9 KB | 17 May 2005 |
| ddr_controller/netlist_rtl/runme | 574 bytes | 17 May 2005 |
| ddr_controller/netlist_rtl/simulation/modelsim/rtl_ddr_controller.vo | 1.3 MB | 17 May 2005 |
| ddr_controller/netlist_rtl/simulation/modelsim/rtl_ddr_controller_modelsim.xrf | 138.1 KB | 17 May 2005 |
| ddr_controller/netlist_rtl/simulation/modelsim/rtl_ddr_controller_v.sdo | 919.5 KB | 17 May 2005 |
| ddr_controller/netlist_rtl/simulation/verilogxl/rtl_ddr_controller.vo | 1.3 MB | 17 May 2005 |
| ddr_controller/netlist_rtl/simulation/verilogxl/rtl_ddr_controller_v.sdo | 919.5 KB | 17 May 2005 |
| ddr_controller/readme.txt | 15.1 KB | 17 May 2005 |
| ddr_controller/stratixii_atoms.v | 489.0 KB | 17 May 2005 |
| ddr_controller/tb/ddr_controller_task.v | 69.8 KB | 17 May 2005 |
| ddr_controller/tb/defines.v | 4.0 KB | 17 May 2005 |
| ddr_controller/tb/tb.v | 46.3 KB | 17 May 2005 |
| ddr_controller/tb/tb_top.v | 30.9 KB | 17 May 2005 |
| ddr_controller/tb/timing.v | 142 bytes | 17 May 2005 |
| ddr_controller/xilinx_functional_rtl/BUFG.v | 120 bytes | 17 May 2005 |
| ddr_controller/xilinx_functional_rtl/DCM.v | 27.6 KB | 17 May 2005 |
| ddr_controller/xilinx_functional_rtl/DdrCntrlTop.v | 35.7 KB | 17 May 2005 |
| ddr_controller/xilinx_functional_rtl/FDDRRSE.v | 1.5 KB | 17 May 2005 |
| ddr_controller/xilinx_functional_rtl/FIFO_GENERATOR_V1_1.v | 240.9 KB | 17 May 2005 |
| ddr_controller/xilinx_functional_rtl/bidircomp.v | 3.4 KB | 17 May 2005 |
| ddr_controller/xilinx_functional_rtl/bidircomp_add.v | 3.4 KB | 17 May 2005 |
| ddr_controller/xilinx_functional_rtl/config_ddr.v | 5.0 KB | 17 May 2005 |
| ddr_controller/xilinx_functional_rtl/cycleCntrl.v | 12.3 KB | 17 May 2005 |
| ddr_controller/xilinx_functional_rtl/dcm_inst.v | 1.1 KB | 17 May 2005 |
| ddr_controller/xilinx_functional_rtl/fifo.edn | 15.7 KB | 17 May 2005 |
| ddr_controller/xilinx_functional_rtl/fifo.v | 5.1 KB | 17 May 2005 |
| ddr_controller/xilinx_functional_rtl/fifo.veo | 3.1 KB | 17 May 2005 |
| ddr_controller/xilinx_functional_rtl/fifo.xco | 2.4 KB | 17 May 2005 |
| ddr_controller/xilinx_functional_rtl/fifo.xcp | 1.2 KB | 17 May 2005 |
| ddr_controller/xilinx_functional_rtl/fifoCntrl.v | 11.1 KB | 17 May 2005 |
| ddr_controller/xilinx_functional_rtl/fifo_fifo_generator_v1_1_as_1.ngc | 31.2 KB | 17 May 2005 |
| ddr_controller/xilinx_functional_rtl/fifo_flist.txt | 118 bytes | 17 May 2005 |
| ddr_controller/xilinx_functional_rtl/glbl.v | 145 bytes | 17 May 2005 |
| ddr_controller/xilinx_functional_rtl/portCntrlRead.v | 7.2 KB | 17 May 2005 |
| ddr_controller/xilinx_functional_rtl/portCntrlWrite.v | 23.5 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/pandr/BUILD/DdrCntrlTop.bld | 2.2 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/pandr/BUILD/DdrCntrlTop.edf | 586.8 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/pandr/BUILD/DdrCntrlTop.ngd | 423.5 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/pandr/BUILD/DdrCntrlTop.ngo | 220.2 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/pandr/BUILD/DdrCntrlTop.ucf | 140 bytes | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/pandr/BUILD/fifo.edn | 15.7 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/pandr/BUILD/fifo.ngo | 8.8 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/pandr/BUILD/fifo_fifo_generator_v1_1_as_1.ngc | 31.2 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/pandr/BUILD/netlist.lst | 207 bytes | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/pandr/MAP/DdrCntrlTop.mrp | 47.4 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/pandr/MAP/DdrCntrlTop.ncd | 73.8 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/pandr/MAP/DdrCntrlTop.ngd | 423.5 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/pandr/MAP/DdrCntrlTop.ngm | 880.5 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/pandr/MAP/DdrCntrlTop.pcf | 39.4 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/pandr/PAR/DdrCntrlTop.ncd | 150.8 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/pandr/PAR/DdrCntrlTop.ngm | 880.5 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/pandr/PAR/DdrCntrlTop.nlf | 1.3 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/pandr/PAR/DdrCntrlTop.pad | 45.4 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/pandr/PAR/DdrCntrlTop.par | 6.5 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/pandr/PAR/DdrCntrlTop.pcf | 39.4 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/pandr/PAR/DdrCntrlTop.sdf | 1.6 MB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/pandr/PAR/DdrCntrlTop.twr | 52.0 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/pandr/PAR/DdrCntrlTop.v | 1.1 MB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/pandr/PAR/DdrCntrlTop.xpi | 45 bytes | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/pandr/PAR/DdrCntrlTop_pad.csv | 45.4 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/pandr/PAR/DdrCntrlTop_pad.txt | 177.6 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/pandr/XCF/DdrCntrlTop.edf | 586.8 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/pandr/fifo.ngo | 8.8 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/pandr/fifo_fifo_generator_v1_1_as_1.ngc | 31.2 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/rev_1/DdrCntrlTop.edf | 586.8 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/rev_1/DdrCntrlTop.fse | 1.6 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/rev_1/DdrCntrlTop.ncf | 15.3 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/rev_1/DdrCntrlTop.plg | 885 bytes | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/rev_1/DdrCntrlTop.srd | 277.9 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/rev_1/DdrCntrlTop.srm | 291.1 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/rev_1/DdrCntrlTop.srr | 73.5 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/rev_1/DdrCntrlTop.srs | 54.3 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/rev_1/DdrCntrlTop.tlg | 4.5 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/rtl/BUFG.v | 122 bytes | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/rtl/DCM.v | 27.6 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/rtl/DdrCntrlTop.v | 34.9 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/rtl/FDDRRSE.v | 1.6 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/rtl/FIFO_GENERATOR_V1_1.v | 240.9 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/rtl/INCA_libs/cds.lib | 26 bytes | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/rtl/INCA_libs/hdl.var | 39 bytes | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/rtl/INCA_libs/worklib/.inca.db.151.lnx86 | 8 bytes | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/rtl/INCA_libs/worklib/cdsinfo.tag | 12 bytes | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/rtl/INCA_libs/worklib/inca.lnx86.151.pak | 632.5 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/rtl/bidircomp.v | 7.4 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/rtl/bidircomp_add.v | 3.5 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/rtl/bidircomp_addbus.v | 6.2 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/rtl/bidircomp_addbus_17.v | 6.2 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/rtl/bidircomp_addbus_18.v | 6.2 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/rtl/bidircomp_addbus_19.v | 6.2 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/rtl/bidircomp_addbus_20.v | 6.2 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/rtl/config_ddr.v | 4.7 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/rtl/coregen.prj | 10.2 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/rtl/cycleCntrl.v | 12.9 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/rtl/dcm_inst.v | 1.1 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/rtl/fifo.edn | 15.7 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/rtl/fifo.v | 5.1 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/rtl/fifo.veo | 3.1 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/rtl/fifo.xco | 2.4 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/rtl/fifo.xcp | 1.2 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/rtl/fifoCntrl.v | 10.1 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/rtl/fifo_fifo_generator_v1_1_as_1.ngc | 31.2 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/rtl/fifo_flist.txt | 118 bytes | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/rtl/glbl.v | 145 bytes | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/rtl/portCntrlRead.v | 6.4 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/rtl/portCntrlWrite.v | 23.3 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/syn/DdrCntrlTop.bld | 854 bytes | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/syn/DdrCntrlTop.log | 807 bytes | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/syn/DdrCntrlTop.ngo | 341.9 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/syn/DdrCntrlTop.prd | 279 bytes | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/syn/DdrCntrlTop.prj | 1.2 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/syn/DdrCntrlTop.tcl | 290 bytes | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/syn/coregen.prj | 10.2 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/syn/netlist.lst | 64 bytes | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/syn/runme | 72 bytes | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth36/syn/runpar | 733 bytes | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/pandr/BUILD/DdrCntrlTop.bld | 2.1 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/pandr/BUILD/DdrCntrlTop.edf | 880.0 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/pandr/BUILD/DdrCntrlTop.ngd | 671.2 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/pandr/BUILD/DdrCntrlTop.ngo | 342.9 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/pandr/BUILD/DdrCntrlTop.ucf | 854 bytes | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/pandr/BUILD/DdrCntrlTop.ucf~ | 818 bytes | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/pandr/BUILD/fifo.edn | 15.7 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/pandr/BUILD/fifo.ngo | 8.8 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/pandr/BUILD/fifo_fifo_generator_v1_1_as_1.ngc | 31.2 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/pandr/BUILD/netlist.lst | 207 bytes | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/pandr/MAP/DdrCntrlTop.mrp | 66.7 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/pandr/MAP/DdrCntrlTop.ncd | 113.2 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/pandr/MAP/DdrCntrlTop.ngd | 671.2 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/pandr/MAP/DdrCntrlTop.pcf | 64.4 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/pandr/PAR/DdrCntrlTop.ncd | 239.6 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/pandr/PAR/DdrCntrlTop.nlf | 1.3 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/pandr/PAR/DdrCntrlTop.pad | 48.1 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/pandr/PAR/DdrCntrlTop.par | 6.4 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/pandr/PAR/DdrCntrlTop.pcf | 64.4 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/pandr/PAR/DdrCntrlTop.sdf | 2.5 MB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/pandr/PAR/DdrCntrlTop.twr | 35.9 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/pandr/PAR/DdrCntrlTop.v | 1.7 MB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/pandr/PAR/DdrCntrlTop.xpi | 45 bytes | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/pandr/PAR/DdrCntrlTop_pad.csv | 48.1 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/pandr/PAR/DdrCntrlTop_pad.txt | 177.6 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/pandr/XCF/DdrCntrlTop.edf | 880.0 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/pandr/fifo.ngo | 8.8 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/pandr/fifo_fifo_generator_v1_1_as_1.ngc | 31.2 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/rev_1/DdrCntrlTop.edf | 880.0 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/rev_1/DdrCntrlTop.fse | 1.6 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/rev_1/DdrCntrlTop.ncf | 22.7 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/rev_1/DdrCntrlTop.plg | 886 bytes | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/rev_1/DdrCntrlTop.srd | 356.8 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/rev_1/DdrCntrlTop.srm | 369.0 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/rev_1/DdrCntrlTop.srr | 93.2 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/rev_1/DdrCntrlTop.srs | 61.4 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/rev_1/DdrCntrlTop.tlg | 4.3 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/rtl/BUFG.v | 122 bytes | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/rtl/DCM.v | 27.6 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/rtl/DdrCntrlTop.v | 30.2 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/rtl/FDDRRSE.v | 1.6 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/rtl/FIFO_GENERATOR_V1_1.v | 240.9 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/rtl/INCA_libs/cds.lib | 26 bytes | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/rtl/INCA_libs/hdl.var | 39 bytes | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/rtl/INCA_libs/snap.nc/.hard.args | 15 bytes | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/rtl/INCA_libs/snap.nc/cds.lib | 20 bytes | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/rtl/INCA_libs/snap.nc/hdl.var | 130 bytes | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/rtl/INCA_libs/worklib/.inca.db.151.lnx86 | 8 bytes | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/rtl/INCA_libs/worklib/cdsinfo.tag | 12 bytes | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/rtl/INCA_libs/worklib/inca.lnx86.151.pak | 631.2 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/rtl/bidircomp.v | 7.4 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/rtl/bidircomp_add.v | 3.5 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/rtl/bidircomp_addbus.v | 6.2 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/rtl/bidircomp_addbus_17.v | 6.2 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/rtl/bidircomp_addbus_18.v | 6.2 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/rtl/bidircomp_addbus_19.v | 6.2 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/rtl/bidircomp_addbus_20.v | 6.2 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/rtl/config_ddr.v | 3.8 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/rtl/coregen.prj | 10.2 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/rtl/cycleCntrl.v | 13.9 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/rtl/d.v | 30.1 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/rtl/dcm_inst.v | 1.1 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/rtl/fifo.edn | 15.7 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/rtl/fifo.v | 5.1 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/rtl/fifo.veo | 3.1 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/rtl/fifo.xco | 2.4 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/rtl/fifo.xcp | 1.2 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/rtl/fifoCntrl.v | 9.9 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/rtl/fifo_fifo_generator_v1_1_as_1.ngc | 31.2 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/rtl/fifo_flist.txt | 118 bytes | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/rtl/glbl.v | 145 bytes | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/rtl/portCntrlRead.v | 6.4 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/rtl/portCntrlWrite.v | 23.3 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/syn/DdrCntrlTop.bld | 854 bytes | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/syn/DdrCntrlTop.log | 723 bytes | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/syn/DdrCntrlTop.ngo | 341.9 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/syn/DdrCntrlTop.prj | 921 bytes | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/syn/DdrCntrlTop.tcl | 290 bytes | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/syn/coregen.prj | 10.2 KB | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/syn/netlist.lst | 64 bytes | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/syn/runme | 72 bytes | 17 May 2005 |
| ddr_controller/xilinx_netlist_rtl_datawidth72/syn/runpar | 733 bytes | 17 May 2005 |
How to Update DDR Controller Device Drivers Quickly & Easily
Step 1 - Download Your Driver
To get the DDR Controller driver, click the green download button above. After you complete your download, move on to Step 2.
If the driver listed is not the right version or operating system, search our driver archive for the correct version. Enter Cypress Semiconductor DDR Controller into the search box above and then submit. In the results, choose the best match for your PC and operating system.
Tech Tip: If you are having trouble deciding which is the right driver, try the Driver Update Utility for Cypress Semiconductor DDR Controller. It is a software utility which automatically finds and downloads the right driver.
Step 2 - Install Your Driver
Once you have downloaded your new driver, you'll need to install it. In Windows, use a built-in utility called Device Manager, which allows you to see all of the devices recognized by your system, and the drivers associated with them.
How to Open Device Manager
In Windows 11, Windows 10 & Windows 8.1, right-click the Start menu and select Device Manager
In Windows 8, swipe up from the bottom, or right-click anywhere on the desktop and choose "All Apps" -> swipe or scroll right and choose "Control Panel" (under Windows System section) -> Hardware and Sound -> Device Manager
In Windows 7, click Start -> Control Panel -> Hardware and Sound -> Device Manager
In Windows Vista, click Start -> Control Panel -> System and Maintenance -> Device Manager
In Windows XP, click Start -> Control Panel -> Performance and Maintenance -> System -> Hardware tab -> Device Manager button
How to Install a driver from Device Manager
Locate the device and model that is having the issue and double-click on it to open the Properties dialog box.
Select the Driver tab.
Click the Update Driver button and follow the instructions.
In most cases, you will need to reboot your computer in order for the driver update to take effect.
Tech Tip: Driver downloads and updates come in a variety of file formats with different file extensions. For example, you may have downloaded an EXE, INF, ZIP, or SYS file. Each file type has a slighty different installation procedure to follow.
For more help, visit our Driver Support Page for step-by-step videos on how to install drivers for every file type.